STM32H533CE datasheet(41/231 Pages) STMICROELECTRONICS

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DS14539 Rev 1

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STM32H533xx

Functional overview

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8/10/12/14-bit progressive video: monochrome or raw Bayer

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YCbCr 4:2:2 progressive video

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RGB 565 progressive video

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Compressed data: JPEG

3.27

Parallel synchronous slave interface (PSSI)

The PSSI peripheral and the DCMI (digital camera interface) use the same circuitry. As a

result, these two peripherals cannot be used at the same time: when using the PSSI, the

DCMI registers cannot be accessed, and vice versa. In addition, the PSSI and the DCMI

share the same alternate functions and the same interrupt vector.

The PSSI is a generic synchronous 8-/16-bit parallel data input/output slave interface. It

enables the transmitter to send a data valid signal that indicates when the data is valid, and

the receiver to output a flow control signal that indicates when it is ready to sample the data.

The PSSI peripheral main features are the following:

•

Slave mode operation

•

8-bit or 16-bit parallel data input or output

•

4-word (16-byte) FIFO

•

Data enable (PSSI_DE) alternate function input and ready (PSSI_RDY) alternate

function output

When selected, these inputs can either enable the transmitter to indicate when the data is

valid, or allow the receiver to indicate when it is ready to sample the data, or both.

3.28

True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the

application as 32-bit samples. It is composed of a live entropy source (analog) and an

internal conditioning component.

The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a

non-deterministic random bit generator (NDRBG).

The true random generator:

•

delivers 32-bit true random numbers, produced by an analog entropy source

conditioned by a NIST SP800-90B approved conditioning stage

•

can be used as entropy source to construct a non-deterministic random bit generator

(NDRBG)

•

produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz

(256 RNG clock cycles otherwise)

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embeds start-up and NIST SP800-90B approved continuous health tests (repetition

count and adaptive proportion tests), associated with specific error management

•

can be disabled to reduce power consumption, or enabled with an automatic low-power

mode (default configuration)

•

has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses

only (else an AHB bus error is generated, and the write accesses are ignored)

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