AD4884BBCZ datasheet(46/116 Pages) AD

46 / 116 page

Data Sheet

AD4884

APPLICATIONS INFORMATION

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Rev. 0 | 46 of 116

The example shows echo clock mode being used, which aids

in data alignment for the host controller (in the case a field-pro-

grammable gate array (FPGA)). When both channels are clocked

simultaneously, it is also feasible to use a single DCO±ChX pair

to synchronize the two data interfaces. In self clock mode, where

DCO±ChX are not available for alignment, the ADC Result La-

tency and LVDS Interface Alignment section describes how the

INTF_CHK_EN bit (Address 0x15, Bit 4) can be enabled to help

align the host controller to data and to mitigate against any system

propagation delays.

Figure 83. Single Lane, LVDS Data Interface Clocking Example

Figure 84. Dual Lane, LVDS Data Interface Clocking Example

In cases where the SPI data interface (see the SPI Data Interface

section) is used to access conversion results from the result

FIFO (see the Result FIFO section) again, it is important that

the CNV±ChX source jitter is carefully considered to achieve the

required performance. In the case shown in the SPI data interface

clocking example (see Figure 85) , an oscillator directly provides

the conversion clock to both channels, and the data is asynchro-

nously clocked from the FIFO by a microcontroller unit (MCU).

Optionally, as shown in Figure 85, the general-purpose input and

output pins can be configured to control the result FIFO operation

(see the GPIO Pins section and the Result FIFO section).

Figure 85. SPI Data Interface Clocking Example, x2 SPI Ports

Figure 86. SPI Data Interface Clocking Example, Shared SPI Bus

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