AD4884BBCZ datasheet(17/116 Pages) AD

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Data Sheet

AD4884

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. 0 | 17 of 116

Table 6. Pin Function Descriptions (Continued)

Pin Number

Mnemonic

Type1

Description

DCO+ChB

Channel B ADC LVDS Echo Clock Positive Output.

This output pin, along with DCO−ChB, outputs a buffered and delayed version of CLK+ChB and CLK−ChB.

Data outputs from LVDS Data Lanes (DA±ChB and DB±ChB, if active) are clocked out in alignment with

both rising and falling edges of DCO+ChB and DCO−ChB. If the echo clock mode is disabled, these pins

can be left unconnected.

DA+ChB/SDOAChB

Channel B ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA−ChB serves as the primary LVDS

Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output A (SDOAChB), which is active in a

4-lane configuration only. Result data is shifted out of this pin on the falling edge of the data interface

clock (DCLKChB).

This pin must left unconnected if not being used.

DA−ChB/SDOBChB

Channel B ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA+ChB serves as the primary LVDS

Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output B (SDOBChB), which is active in a

4-lane configuration only. Result data is shifted out of this pin on the falling edge of the data interface

clock (DCLKChB).

This pin must left unconnected if not being used.

SCLKChA

Channel A ADC Configuration Interface Serial Data Clock. This clock input is used to shift data into and

out of the device configuration memory.

P10

SDIChA

Channel A ADC Configuration Interface Serial Data Input. Data is shifted into this input on the rising edge

of the serial data clock, SCLKChA.

P11

CS ChA

Channel A ADC Configuration Interface Chip-Select Input (Active Low). The CSChA input frames serial

data transfers over the Configuration SPI.

P12

DCO+ChA

Channel A ADC LVDS Echo Clock Positive Output.

This pin, along with DCO−ChB, outputs a buffered and delayed version of CLK+ChA and CLK−ChA. Data

outputs from LVDS Data Lanes (DA±ChA and DB±ChA, if active) are clocked out in alignment with both

rising and falling edges of DCO+ChA and DCO−ChA. If the echo clock mode is disabled, these pins can be

left unconnected.

P13

DA+ChA/SDOAChA

Channel A ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA−ChA serves as the primary LVDS

Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output A (SDOAChA), which is active in a

4-lane configuration only. Result data is shifted out of this pin on the falling edge of the data interface

clock (DCLKChA).

This pin must left unconnected if not being used.

P14

DA−ChA/SDOBChA

Channel A ADC Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA+ChA serves as the primary LVDS

Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output B (SDOBChA), which is active in a

4-lane configuration only. Result data is shifted out of this pin on the falling edge of the data interface

clock (DCLKChA).

This pin must left unconnected if not being used.

1 AI is analog input, AO is analog output, DI is digital input, DI/O is digital input and output, DO is digital output, and P is power.

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