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TAS5706PAPR 데이터시트(PDF) 24 Page - Texas Instruments

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부품명 TAS5706PAPR
상세설명  20-W Stereo Digital Audio Power Amplifier with EQ and DRC
PDF  62 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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TAS5706PAPR 데이터시트(HTML) 24 Page - Texas Instruments

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I
2S Timing
23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9
8
1
0
0
4
5
1
0
23
22
1
19
18
15
14
MSB
LSB
5
4
9
8
1
0
0
4
5
1
0
SCLK
TAS5706
SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64
× f
S is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 30. I2S 64-fS Format
24
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TAS5706



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