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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SMC032AF 데이터시트(PDF) 39 Page - Numonyx B.V |
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SMC032AF 데이터시트(HTML) 39 Page - Numonyx B.V |
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39 / 82 page  SMCxxxAF Software interface 39/82 7 Software interface 7.1 CF-ATA Drive register set definition and protocol The CompactFlash memory card can be configured as a high performance I/O device through: ● Standard PC-AT disk I/O address spaces – 1F0h-1F7h, 3F6h-3F7h (primary); – 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). ● Any system decoded 16 byte I/O block using any available IRQ. ● Memory space. Communication to or from the card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 35 is a detailed description of these methods: 7.2 Memory mapped addressing (conf = 0) When the card registers are accessed via memory references, the registers appear in the common memory space window: 0-2 Kbytes as shown in Table 36. This window accesses the Data register FIFO. It does not allow random access to the data buffer within the card. Register 0 is accessed with –CE1 and –CE2 Low, as a word register on the combined Odd and Even Data Bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature bytewide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to address 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer, however repeated byte accesses to register 9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Table 35. I/O configurations Standards configurations Config index I/O or memory Address Description 0 Memory 0h-Fh, 400h-7FFh Memory mapped 1 I/O xx0h-xxFh I/O mapped 16 continuous registers 2 I/O 1F0-1F7h, 3F6h-3F7h Primary I/O mapped 3 I/O 170-177h, 376h-377h Secondary I/O mapped |
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