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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SMC032AF 데이터시트(PDF) 41 Page - Numonyx B.V |
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SMC032AF 데이터시트(HTML) 41 Page - Numonyx B.V |
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41 / 82 page  SMCxxxAF Software interface 41/82 7.3 Contiguous I/O mapped addressing (conf = 1) When the system decodes a contiguous block of I/O registers to select the card, the registers are accessed in the block of I/O space decoded by the system as shown in Table 37. As for the memory mapped addressing, register 0 is accessed with –CE1 Low and –CE2 Low (and A0 Don’t care) as a word register on the combined odd and even data bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of byte accesses to offset 0. The address space of this word register overlaps the address space of the error and feature bytewide registers at offset 1. When accessed twice as byte register with –CE1 Low, the first byte is the even byte of the word and the second is the odd byte. A byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer, however repeated byte accesses to register 9 are not supported. Repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Table 37. Contiguous I/O decoding – REG A10 to A4 A3 A2 A1 A0 Offset – IORD=0 – IOWR=0 0 X 0000 0h Even Data register Even Data register 0 X 0001 1h Error register Feature register 0 X 0010 2h Sector Count register Sector Count register 0 X 0011 3h Sector Number register Sector Number register 0 X 0100 4h Cylinder Low register Cylinder Low register 0 X 0101 5h Cylinder High register Cylinder High register 0 X 0110 6h Select Card/Head register Select Card/Head register 0 X 0111 7h Status register Command register 0 X 1000 8h Dup. Even Data register Dup. Even Data register 0 X 1001 9h Dup. Odd Data register Dup. Odd Data register 0 X 1101 Dh Dup. Error register Dup. Feature register 0 X 1110 Eh Alternate Status register Device Control register 0 X 1111 Fh Drive Address register Reserved |
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