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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SMC032AF 데이터시트(PDF) 44 Page - Numonyx B.V |
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SMC032AF 데이터시트(HTML) 44 Page - Numonyx B.V |
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44 / 82 page  CF-ATA registers SMCxxxAF 44/82 8 CF-ATA registers The following section describes the hardware registers used by the host software to issue commands to the card. These registers are collectively referred to as the ‘task file’. 8.1 Data register (address 1F0h [170h]; offset 0, 8, 9) The data register is a 16-bit register used to transfer data blocks between the card data buffer and the host. This register overlaps the error register. Table 40 describes the combinations of data register access and explains the overlapped data and error/feature registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for word (–CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the word data register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed. 8.2 Error register (address 1F1h [171h]; offset 1, 0Dh read only) This read only register contains additional information about the source of an error when an error is indicated in bit 0 of the status register. The bits are defined in Table 41. This register is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and – CE1 High. 8.2.1 Bit 7 (BBK) This bit is set when a bad block is detected. 8.2.2 Bit 6 (UNC) This bit is set when an uncorrectable error is encountered. 8.2.3 Bit 5 This bit is ‘0’. Table 40. Data register access Data register –CE2 –CE1 A0 Offset Data Bus Word Data register 0 0 X 0, 8, 9 D15 to D0 Even Data register 1 0 0 0, 8 D7 to D0 Odd Data register 1 0 1 9 D7 to D0 Odd Data register 0 1 X 8, 9 D15 to D8 Error/Feature register 1 0 1 1, Dh D7 to D0 Error/Feature register 0 1 X 1 D15 to D8 Error/Feature register 0 0 X Dh D15 to D8 |
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