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M7040N 데이터시트(PDF) 93 Page - STMicroelectronics |
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M7040N 데이터시트(HTML) 93 Page - STMicroelectronics |
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93 / 159 page ![]() 93/159 M7040N Figure 68. x288 Table with One Device Table 42. Latency of SEARCH from Cycles C and D to SRAM Access Cycle Table 43. Shift of SSF and SSV from SADR # of devices Max Table Size Latency in CLK Cycles 1 (TLSZ = 00) 16K x 288-bit 4 2–8 (TLSZ = 01) 128K x 288-bit 5 2–31 (TLSZ = 10) 496K x 288-bit 6 CFG = 1010101010101010 0 4 8 12 16380 (288-bit Configuration) Location address L 287 0 K GMR 287 0 AI04714 (First matching entry) 0 12 3 BC D A HLAT Number of CLK Cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 |
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