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M7040N 데이터시트(PDF) 24 Page - STMicroelectronics |
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M7040N 데이터시트(HTML) 24 Page - STMicroelectronics |
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24 / 159 page ![]() M7040N 24/159 SEARCH-Successful Registers (SSR[0:7]) The device contains eight search successful reg- isters (SSRs) to hold the index of the location where a successful search occurred. The format of each register is described in Table 10. The SEARCH command specifies which SSR stores the index of a specific SEARCH command in Cy- cle B of the SEARCH Instruction. Subsequently, the host ASIC can use this register to access that data array, mask array, or external SRAM using the index as part of the indirect access address (see Table 20, page 34 and Table 23, page 37) . The device with a valid bit set performs a READ or WRITE operation. All other devices suppress the operation. Table 10. SEARCH-Successful Register (SSR) Description Field Range Initial Value Description INDEX [15:0] X Index. This is the address of the 72-bit entry where a successful search occurs. The device updates this field only when a search is successful. If a hit occurs in a 144-bit entry-size quadrant, the LSB is '0.' If a hit occurs in a 288-bit entry size quadrant, the two LSBs are '00.' This index updates if the device is either a local or global winner in a SEARCH operation. – [30:16] 0 Reserved. VALID [31] 0 Valid. During SEARCH operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to '1.' This bit updates only when the device is a global winner in a SEARCH operation. – [71:32] 0 Reserved. |
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