M7040N datasheet(49/159 Pages) STMICROELECTRONICS

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M7040N

The following is the sequence of operation for a

single 72-bit SEARCH command (also refer to

Command Codes, page 30).

– Cycle A: The host ASIC drives the CMDV high

and applies SEARCH command code ('10') on

CMD[1:0] signals. {CMD[10],CMD[5:3]} signals

must be driven with the index to the GMR pair

for use in this SEARCH operation. CMD[8:6]

signals must be driven with the same bits that

will be driven on SADR[23:21] by this device if it

has a hit. DQ[71:0] must be driven with the 72-

bit data to be compared. The CMD[2] signal

must be driven to a logic '0.'

– Cycle B: The host ASIC continues to drive the

CMDV high and applies SEARCH command

('10') on CMD[1:0]. CMD[5:2] must be driven by

the index of the comparand register pair for stor-

ing the 144-bit word presented on the DQ Bus

during Cycles A and B. CMD[8:6] signals must

be driven with the index of the SSR that will be

used for storing the address of the matching en-

try and the Hit Flag (see SEARCH-Successful

Registers (SSR[0:7]), page 24). The DQ[71:0]

continues to carry the 72-bit data to be com-

pared.

Note: For 72-bit searches, the host ASIC must

supply the same 72-bit data on DQ[71:0] during

both Cycles A and B. The even and odd pair of

GMRs selected for the comparison must be pro-

grammed with the same value.

The logical 72-bit SEARCH operation is shown in

Figure 32, page 52. The entire table (31 devices of

72-bit entries) is compared to a 72-bit word K (pre-

sented on the DQ Bus in both Cycles A and B of

the command) using the GMR and the local mask

bits. The effective GMR is the 72-bit word speci-

fied by theidentical valueinbothevenand odd

GMR pairs in each of the eight devices and select-

ed by the GMR Index in the command’s Cycle A.

The 72-bit word K (presented on the DQ Bus in

both Cycles A and B of the command) is also

stored in both even and odd comparand register

pairs in each of the eight devices and selected by

the Comparand Register Index in command’sCy-

cle B. In the x72 configuration, the even com-

parand register can be subsequently used by the

LEARN command only in the first non-full device.

The word K (presented on the DQ Bus in both Cy-

cles A and B of the command) is compared with

each entry in the table starting at location “0.” The

first matching entry’s location address, “L,” is the

winning address that is driven as part of the SRAM

address on the SADR[23:0] lines (see SRAM AD-

DRESSING, page 128). The global winning device

will drive the bus in a specific cycle. On global miss

cycles the device with LRAM = 1 and LDEV = 1 will

be the default driver for such missed cycles.

The SEARCH command is a pipelined operation

and executes a search at half the rate of the fre-

quency of CLK2X for 72-bit searches in x72-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 72-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 32, page 64.

Forup to 31devices in thetable(TLSZ =10),

search latency from command to SRAM access

cycle is 6. In addition, SSV and SSF shift further to

the right for different values of HLAT, as specified

in Table 33, page 64.

The 72-bit SEARCH operation is pipelined and ex-

ecutes as follows:

– Four cycles from the SEARCH command, each

of the devices knows the outcome internal to it

for that operation;

– In the fifth cycle after the SEARCH command,

the devices in a block arbitrate for a winner

amongst them (a “block” being defined as less

than or equal to eight devices resolving the win-

ner within them using the LHI[6:0] and LHO[1:0]

signalling mechanism);

– In the sixth cycle after the SEARCH command,

the blocks (of devices) resolve the winning block

through the BHI[2:0] and BHO[2:0] signalling

mechanism. The winning device within the win-

ning block is the global winning device for a

SEARCH operation.

Table 31. Hit/Miss Assumption

Search Number

Block 0

Miss

Block 1

Miss

Hit

Miss

Block 2

Miss

Hit

Miss

Block 3

Hit

Miss

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