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M7040N 데이터시트(PDF) 41 Page - STMicroelectronics |
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M7040N 데이터시트(HTML) 41 Page - STMicroelectronics |
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41 / 159 page ![]() 41/159 M7040N Figure 24. x72 Table with One Device Table 26. Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit Table 27. Shift of SSF and SSV from SADR # of devices Max Table Size Latency in CLK Cycles 1 (TLSZ = 00) 64K x 72-bit 4 2–8 (TLSZ = 01) 512K x 72-bit 5 2–31 (TLSZ = 10) 1984K x 72-bit 6 Comparand Register (even) Comparand Register (odd) 71 0 K CFG = 0000000000000000 0 1 2 3 65535 (288-bit Configuration) Location address L K Comparand Register (even) 71 0 K GMR 71 0 AI04678 (First matching entry) HLAT Number of CLK Cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 |
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