CHR71000 datasheet(25/54 Pages) AMSOSRAM

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CHR71000

Functional description

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DS000427 • v2-01 • 2026-Mar-18

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Where ROT is expressed in number of master clock periods (see point 7.3.2.2 for more

details). So, for a full image with a 30MHz clock and a ROT of 168 clock cycles (default), you

can achieve a 2.98fps frame rate.

The global active-low reset (RESET_N) resets all digital sequential cells (flip-flops) in the

sensor. A falling edge on the RESET_N input (enter reset state) is fed to all sequential cells

asynchronously.

A rising edge on the RESET_N input (exit reset state) is synchronized internally to the rising

edge of CLK_IN (the 3rd one after the rising edge of the reset signal) before it goes to the flip-

flops. This ensures that all flip-flops exit the reset state during the same clock period.

The reset synchronization circuit also ensures that the minimum width of an active pulse on

RESET_N is 2 clock cycles on the internal reset_n. This means that every glitch on the

RESET_N input will generate a complete reset of the device. Figure 12 shows the timing of the

reset synchronization circuit.

Figure 12: LVDS clock delay versus master clock

CLK_IN

RESET_N

Internal reset_n

CHR71000 데이터시트(PDF) 25 Page - ams-OSRAM AG