CHR71000 datasheet(38/54 Pages) AMSOSRAM

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CHR71000

Functional description

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DS000427 • v2-01 • 2026-Mar-18

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7.5.2

SPI read

When the control bit is ‘0’, the address bits are clocked in. The data bits on the SPI_DIN bus

are ignored. The data bits in the on-chip register indicated by the address bits are clocked out

(SPI_DOUT) at each falling edge of the clock with a fixed delay of 75ns from the last falling

SPI clock edge of the address. Therefor it is recommended to sample the read out bytes in at

the falling SPI clock edge.

If SPI_ENA is made low, the SPI logic immediately resets to an idle state. All transferred bits

during the active transfer will be lost. When writing and/or reading multiple registers

sequentially, it is allowed to keep SPI_ENA high in-between two transfers. Doing so allows you

to continuously read/write data, without a time gap between transfers.

Figure 20: SPI read timing

Table 12: SPI reading timing

Time

Description

Requirement

spi_ena setup time before rising edge of spi_clk

Min 0.5x spi_clk period

spi_din setup time before rising edge of spi_clk

Min 0.25x spi_clk period

SPI clock period

Min 4x master clock period

SPI_CLK

SPI_ENA

SPI_DIN

SPI_DOUT

C=0

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

75ns

133ns @ 7.5MHz

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