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CHR71000 데이터시트(PDF) 42 Page - ams-OSRAM AG

부품명 CHR71000
상세설명  CHR71000 High resolution 70 MP CMOS image sensor
PDF  54 Pages
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제조업체  AMSOSRAM [ams-OSRAM AG]
홈페이지  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

CHR71000 데이터시트(HTML) 42 Page - ams-OSRAM AG

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CHR71000
Register description
Datasheet • PUBLIC • Document Feedback
DS000427 • v2-01 • 2026-Mar-18
42 / 54
/
8
Register description
8.1
Register overview
The next table shows the register map of the sensor.
The first column of the table gives the address that needs to be uploaded during an SPI
transfer to interface with the register. Every register address represents 8 register bits. The
second column of the table lists which of the 8 bits of the address are used by the register. The
last column contains the value the register should be set to after boot up or reset. They can
differ from the default startup value of the register.
A number of registers is reserved for internal use only.
Table 13: Register overview
Addr
Bits
Name
Description
Default
Recommended
0
[7:0]
reg_addr_x_start[7:0]
Start address in x direction
1
1
1
[7:0]
reg_addr_x_end[7:0]
End address in x direction
114
114
2
[7:0]
reg_addr_x_step[7:0]
Step of moving window in x direction
0
0
3
[1:0]
reg_addr_x_start[9:8]
MSB of address setting
0
0
[3:2]
reg_addr_x_end[9:8]
MSB of address setting
2
2
[5:4]
reg_addr_x_step[9:8]
MSB of address setting
0
0
4
[7:0]
reg_addr_y_start[7:0]
Start address in y direction
1
1
5
[7:0]
reg_addr_y_end[7:0]
End address in y direction
120
120
6
[7:0]
reg_addr_y_step[7:0]
Step of moving window in y direction
0
0
7
[1:0]
reg_addr_y_start[9:8]
MSB of address setting
0
0
[3:2]
reg_addr_y_end[9:8]
MSB of address setting
3
3
[5:4]
reg_addr_y_step[9:8]
MSB of address setting
0
0
8
[7:0]
reg_inte_time[7:0]
Set integration time
181
181
9
[7:0]
reg_inte_time[15:8]
MSB of integration time
27
27
10
[7:0]
reg_inte_time[23:16]
MSB of integration time
0
0
11
[7:0]
reg_nrof_frames[7:0]
Set number of frames in burst
1
1
12
[7:0]
reg_nrof_frames[15:8]
MSB of number of frames in burst
0
0
13
[0]
reg_seq_enable
Enable internal sequencer
0
0
[1]
reserved
/
0
0
[2]
reserved
/
0
0
[3]
reserved
/
1
1



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