CHR71000 datasheet(37/54 Pages) AMSOSRAM

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CHR71000

Functional description

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DS000427 • v2-01 • 2026-Mar-18

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7.5

SPI programming

The register block contains an SPI register interface and the array of registers that are used for

the chip programmability. Each register is 8-bit wide and can be individually addressed for read

and write.

Data is always captured on the rising edge of SPI_CLK. When reading data from the sensor,

the sensor launches data after the rising edge of SPI_CLK. It shall be captured on the next

rising edge of SPI_CLK.

Because the SPI clock is internally sampled by the master clock, it should be 4x slower than

the input master clock. This means that for a 30 MHz master clock, the SPI clock frequency is

7.5MHz. The edges of the SPI clock should coincide with the falling edges of the master clock.

Also note that the master clock input should always be running when doing a SPI transfer.

The SPI I/O’s will not be tri-stated when not active.

7.5.1

SPI write

Data bits are written at each rising edge of the SPI clock (SPI_CLK). The control bit that is

clocked in first on the SPI_DIN line is used to indicate a write or read access cycle.

In case this control bit is ‘1’, the data bits are written into the on-chip registers as described

above.

Figure 19: SPI write timing

SPI_CLK

SPI_ENA

SPI_DIN

SPI_DOUT

C=1

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

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