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R7KA8M2AFECAC 데이터시트(PDF) 214 Page - Renesas Technology Corp

부품명 R7KA8M2AFECAC
상세설명  Renesas Microcontrollers
PDF  295 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Table 2.80
ESWM timing (MII)
Conditions:
1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: ETn_MDC, ETn_MDIO.
2. The drive capacity selection and voltage range for pins other than ETn_MDC, ETn_MDIO.
● MII use only: Middle drive select, VCC = 2.7 to 3.6
● GMII and MII use: RGMII 2.50 V drive select, VCC = 2.3 to 2.7
● GMII and MII use: RGMII 3.30 V drive select, VCC = 3.0 to 3.6
Parameter
Symbol
VCC
Min
Max
Unit
Test
conditions
ESWM (MII)
ETn_TX_CLK cycle time
tTcyc
2.30 V or
above
40
—
ns
—
ETn_TX_EN output delay
tTENd
1
20
ns
Figure 2.113
ETn_ETXD0 to ETn_ETXD3
output delay
tMTDd
1
20
ns
ETn_RX_CLK cycle time
tTRcyc
40
—
ns
—
ETn_RX_DV setup time
tRDVs
10
—
ns
Figure 2.114
ETn_RX_DV hold time
tRDVh
10
—
ns
ETn_ERXD0 to ETn_ERXD3
setup time
tMRDs
10
—
ns
ETn_ERXD0 to ETn_ERXD3
hold time
tMRDh
10
—
ns
ETn_RX_ER setup time
tRERs
10
—
ns
ETn_RX_ER hold time
tRESh
10
—
ns
ETn_TX_CLK
ETn_TX_EN
ETn_ETXD0 to
ETn_ETXD3
SFD
DATA
CRC
Preamble
tTENd
tMTDd
Figure 2.113
MII transmission timing in normal operation
Preamble
DATA
CRC
SFD
tRDVs
tMRDs
tMRDh
tRDVh
ETn_RX_CLK
ETn_RX_DV
ETn_ERXD0 to
ETn_ERXD3
ETn_RX_ER
Figure 2.114
MII reception timing in normal operation
RA8M2 Datasheet
2. Electrical Characteristics
R01DS0438EJ0130 Rev.1.30
Feb 27, 2026
Page 214 of 295



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