R7KA8M2AFECAC datasheet(216/295 Pages) RENESAS

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tSETUP

tHOLD

tHIGH

tLOW

tPERIOD

ETn_GTX_CLK or

ETn_RX_CLK

ETn_TXD[7:0], ETn_TX_EN, ETn_TX_ER or

ETn_RXD[7:0], ETn_RX_DV, ETn_RX_ER

Figure 2.115

GMII timing

GMII Driver

33 ohms

Input Measurement

point

5pF

Transmission Line

1.00ns delay

50 ohms ±15%

Figure 2.116

GMII output timing measurement conditions

Table 2.82

ESWM timing (RGMII)

Conditions:

1. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: ETn_MDC, ETn_MDIO.

2. The drive capacity selection and voltage range for pins other than ETn_MDC, ETn_MDIO.

● RGMII use at 2.5 V: RGMII 2.50V drive select, VCC = 2.3 to 2.7

● RGMII use at 3.3 V: RGMII 3.30V drive select, VCC = 3.0 to 3.6

Parameter

Symbol

VCC

Min

Max

Unit

Test

conditions

ESWM

(RGMII)

Data to Clock output Skew

(at Transmitter)*1

TskewT

2.30 V to

3.60 V

−500

500

Figure 2.117

Figure 2.118

Figure 2.119

Data to Clock input Skew (at

Receiver)*1

TskewR

2.6

Data to Clock output Setup

(at Transmitter-integrated

delay)

TsetupT

1.2

—

Clock to Data output Hold (at

Transmitter–integrated delay)

TholdT

1.2

—

Data to Clock input Setup (at

Receiver–integrated delay)

TsetupR

—

Data to Clock input Hold (at

Receiver–integrated delay)

TholdR

—

Clock Cycle Duration*2

Tcyc

7.2

8.8

Duty Cycle for Gigabit*3

Duty_G

Duty Cycle for 10/100T*3

Duty_T

Rise / Fall Time (20-80%)

Tr / Tf

—

0.75

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 216 of 295

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