R7KA8D2AFDCAC datasheet(77/292 Pages) RENESAS

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Table 2.34

Coremark and normal mode current, CPU0 active, CPU1 Deep Sleep. (DCDC mode and External VDD

mode)

Parameter

Symbol Typ

Max

Unit Test conditions

°C

105

°C

Supply

current*1*2

CPUCLK0 =

1 GHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

IDD

151

—

μA/

CPU1 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK1 = 250 MHz,

MRICLK = 250 MHz, MRPCLK

= 15.6 MHz, ICLK = 250 MHz,

PCLKA = 15.6 MHz, PCLKB =

15.6 MHz, PCLKC = 15.6 MHz,

PCLKD = 15.6 MHz, PCLKE =

15.6 MHz, BCLK = 15.6 MHz

Cache off, executing

from ITCM

143

—

Cache off, executing

from SRAM

—

Cache off, executing

from MRAM

104

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

118

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

121

—

CPUCLK0 =

800 MHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

157

—

μA/

CPU1 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK1 = 200 MHz,

MRICLK = 200 MHz, MRPCLK

= 12.5 MHz, ICLK = 200 MHz,

PCLKA = 12.5 MHz, PCLKB =

12.5 MHz, PCLKC = 12.5 MHz,

PCLKD = 12.5 MHz, PCLKE =

12.5 MHz, BCLK = 12.5 MHz

Cache off, executing

from ITCM

149

—

Cache off, executing

from SRAM

—

Cache off, executing

from MRAM

111

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

124

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

127

—

CPUCLK0 =

600 MHz

VSCR_2

VCL =

voltage

range 2

Coremark

Cache on

164

—

μA/

CPU1 = Deep Sleep

Graphics and ESWM power

domain off

CPUCLK1 = 150 MHz,

MRICLK = 150 MHz, MRPCLK

= 9.4 MHz, ICLK = 150 MHz,

PCLKA = 9.4 MHz, PCLKB =

9.4 MHz, PCLKC = 9.4 MHz,

PCLKD = 9.4 MHz, PCLKE =

9.4 MHz, BCLK = 9.4 MHz

Cache off, executing

from ITCM

156

—

Cache off, executing

from SRAM

106

—

Cache off, executing

from MRAM

119

—

Normal

mode

All peripheral disabled,

Cache on, while (1)

code

131

—

All peripheral disabled,

Cache off, while (1)

code executing from

MRAM

135

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

RA8D2 Datasheet

2. Electrical Characteristics

R01DS0493EJ0130 Rev.1.30

Feb 27, 2026

Page 77 of 292

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