MK50H27PLCC datasheet(32/56 Pages) STMICROELECTRONICS

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4.2.5 Transmit Descriptor Ring Pointer (continued)

BIT

NAME

DESCRIPTION

Reserved, must be written as a zero.

14:12

TLEN

TRANSMIT RING LENGTH is the number of entries in the Transmit

Ring expressed as a power of two.

TLEN

Number of Entries

416

532

664

128

11:08

Reserved, must be written as a zero.

07:00/15:00

TDRA

TRANSMIT DESCRIPTOR RING ADDRESS is the base address

(lowest address) of the Transmit Descriptor Ring.

The

Transmit

Descriptor Ring Address must begin on a word boundary.

4.2.6 Status Buffer Address

BIT

NAME

DESCRIPTION

15:08

TWS

TRANSMIT WINDOW SIZE is used to determine the maximum number

of MSUs that can be transmitted without acknowledgement. For com-

pliance with Japanese TTC JT-Q703 this value should typically be 40.

For compliance with CCITT/ITU Q.703 this value should be 127.

For

compatibility with the original MK50H27, this field may be programmed

with all zeroes, causing the MK50H27 to use a default value of 127 as

did the MK50H27.

07:00/15:00

SBA

STATUS BUFFER ADDRESS points to the status

buffer into which link status information is placed upon the issuance of

the Status Request primitive by the HOST. The status buffer must be-

gin on a word boundary.

IADR + 44

IADR + 46

SBA<15:00>

SBA<23:16>

TWS <15:08>

MK50H27

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