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MK50H27PLCC 데이터시트(PDF) 46 Page - STMicroelectronics |
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MK50H27PLCC 데이터시트(HTML) 46 Page - STMicroelectronics |
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46 / 56 page ![]() A 16-23 ALE SYSCLK ADDRESS BM0,1 READY DAS HLDA HOLD NOTES: 2. Output delay times are the maximum delay from the specifed edge to a valid output. 3. The Bus Master cycle time will increase from a minimum, in 1 SYSCLK increments until the slave device returns READY. 64 24 25 65 26 27 40 23 23 43 44 41 42 28 22 60 61 T0 T1 T2 T 3 T 4 T5 T6 DAL0-15 READ DALO DALI 29 30 50 32 45 DATA IN ADDR 31 49 48 47 46 48 1. The shaded SYSCLK periods T0 and T5 will be removed when setting CSR2 bit 15, CYCLE =1 to select the shorter DMA cycle as shown in Figure 7a. Figure 7: MK50H27 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) MK50H27 46/56 |
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