ST10 datasheet(32/58 Pages) STMICROELECTRONICS

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ST10F163

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Read/Write active current 4

IRWL

-500

–

µAVOUT =VOLmax

ALE inactive current 4

IALEL

–

µAVOUT =VOLmax

ALE active current 4

IALEH

–

500

µAVOUT = 2.4 V

Port 6 inactive current 4

IP6H

–

-40

µAVOUT = 2.4 V

Port 6 active current4

IP6L

-500

–

µAV

OUT =VOL1max

PORT0 configuration current 4

IP0H

–

-10

µAV

IN =VIHmin

IP0L

-100

–

µAVIN =VILmax

XTAL1 input current

IIL

–

±20

µA0 V < VIN <VDD

Pin capacitance 4 (digital inputs/outputs)

CIO

–

f = 1 MHz

TA =25 °C

Power supply current

ICC

–20 +

3.5 * fCPU

RSTIN = VIL2

fCPU in [MHz]

Idle mode supply current

IID

–10 +

1.2 * fCPU

RSTIN = VIH1

fCPU in [MHz]

Power-down mode supply current

IPD

–50

µA

VDD = 5.5 V

1. ST10F163 pins are equipped with Low-Noise output drivers, which significantly improve the device’s EMI performance. These Low-Noise

drivers deliver their maximum current only until the respective target output level is reached. After that, the output current is reduced. This

results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in

column “Test Conditions” is delivered in any case.

2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage

results from the external circuitry.

3. Not 100% tested, guaranteed by design characterization.

4. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output

and the open drain function is not enabled.

5. The maximum current may be drawn while the respective signal line remains inactive.

6. The minimum current must be drawn in order to drive the respective signal line active.

7. The power supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters

are tested at VDDmax and 25 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demux

16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, Port0 is driven with

the value ‘00CCh’ that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate waitstate, normal ALE.

Peripherals are not activated.

8. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are

tested at VDDmax and 25 MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH.

9. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD – 0.1 V to VDD,

VREF = 0 V, all outputs (including pins configured as outputs) disconnected.

Table 15 : DC Characteristics (continued)

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

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