ST10 datasheet(36/58 Pages) STMICROELECTRONICS

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ST10F163

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The actual minimum value for TCL depends on

the jitter of the PLL. As the PLL is constantly

adjusting its output frequency so it corresponds to

the applied input frequency (crystal or oscillator)

the relative deviation for periods of more than one

TCL is lower than for one single TCL (see formula

and figure below).

For a period of

N * TCL the minimum value is

computed using the corresponding deviation DN:

where

N = number of consecutive TCLs and 1

≤ N

≤ 40. So for a period of 3 TCLs (N = 3):

This is especially important for bus cycles using

waitstates and e.g. for the operation of timers,

serial interfaces, etc. For all slower operations and

longer periods (e.g. pulse train generation or mea-

surement, lower baudrates, etc.) the deviation

caused by the PLL jitter is negligible (see

Figure 12).

XVI.4.8 - Memory cycle variables

The tables below use three variables which are

derived from the BUSCONx registers and repre-

sent the special characteristics of the pro-

grammed memory cycle. The following table

describes, how these variables are to be com-

puted.

TCL

min

TCL

NOM

l 100

⁄

)

–

(

N 15

) %

[]

⁄

–

(

43 15

⁄

–

3.8%

3TCL

min

3TCL

NOM

3.8 100

⁄

–

()

TCL

NOM

0.962

57.72nsec@f

CP U

25MHz

()

Description

Symbol

Values

ALE Extension

TCL * <ALECTL>

Memory Cycle Time Waitstates

2TCL * (15 - <MCTC>)

Memory Tristate Time

2TCL * (1 - <MTTC>)

Figure 12 : Approximated maximum PLL jitter

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

1 < N < 40 and 10MHz < fCPU < 25MHz.

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