ST10 datasheet(45/58 Pages) STMICROELECTRONICS

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ST10F163

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Latched CS low to Valid Data In

t39

–

40 + tC+

2tA

–

3TCL - 20

+tC +2tA

Latched CS hold after RD, WR

t41

6 + tF

–

TCL - 14

+tF

–ns

Address setup to RdCS, WrCS (with RW-delay)

t82

26 + 2tA

–

2TCL - 14

+2tA

–ns

Address setup to RdCS, WrCS (no RW-delay)

t83

6 + 2tA

–

TCL -14

+2tA

–ns

RdCS to Valid Data In (with RW-delay)

t46

–

16 + tC

–

2TCL - 24

+tC

RdCS to Valid Data In (no RW-delay)

t47

–

36 + tC

–

3TCL - 24

+tC

RdCS, WrCS Low Time (with RW-delay)

t48

30 + tC

–

2TCL - 10

+tC

–ns

RdCS, WrCS Low Time (no RW-delay)

t49

50 + tC

–

3TCL - 10

+tC

–ns

Data valid to WrCS

t50

26 + tC

–

2TCL - 14

+tC

–ns

Data hold after RdCS

t51

0–0–

Data float after RdCS (with RW-delay)

t53

–

20 + tF

–

2TCL - 20

+tF

Data float after RdCS (no RW-delay)

t68

–

0 + tF

–

TCL - 20

+tF

Address hold after RdCS, WrCS

t55

-10 + tF

–-10 + tF

–ns

Data hold after WrCS

t57

6 + tF

–

TCL - 14

+tF

–ns

1. RW-delay and tA refer to the following bus cycle.

2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore

address changes before the end of RD have no impact on read cycles

Table 17 : Demultiplexed bus characteristics (continued)

Parameter

Symbol

Max. CPU Clock

= 25MHz

Variable CPU Clock

1/2TCL = 1 to 25MHz

min.

max.

min.

max.

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