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ST10F167 데이터시트(PDF) 63 Page - STMicroelectronics

부품명 ST10F167
상세설명  16-BIT MCU WITH 128K BYTE FLASH MEMORY
PDF  69 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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ST10F167 데이터시트(HTML) 63 Page - STMicroelectronics

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ST10F167
20.5.9 CLKOUT and READY
VDD =5 V ± 5%, VSS =0 V, TA = -40 to +85 °C
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF,CL (for Port 6, CS) = 100 pF
Notes 1:These timings are given for test purposes only, in order to assure recognition at a specific clock
edge.
2:Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum
values. This adds even more time for deactivating READY.
The 2tA and 2tc refer to the next bus cycle, tF refers to the current bus cycle.
Table 20.8
CLKOUT and READY Characteristics
Parameter
Symbol
Max. CPU Clock
=20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
CLKOUT cycle time
t29
CC
50
50
2TCL
2TCL
ns
CLKOUT high time
t
30
CC
20
–
TCL – 5
–
ns
CLKOUT low time
t
31
CC
15
–
TCL – 10
–
ns
CLKOUT rise time
t
32
CC
–
5
–
5
ns
CLKOUT fall time
t
33
CC
–
10
–
10
ns
CLKOUT rising edge to
ALE falling edge
t
34
CC
-5 +
t
A
10 +
t
A
-5 +
t
A
10 +
t
A
ns
Synchronous READY
setup time to CLKOUT
t
35
SR
30
–
30
–
ns
Synchronous READY
hold time after CLKOUT
t
36
SR
0
–
0
–
ns
Asynchronous READY
low time
t37
SR
65
–
2TCL + 15
–
ns
Asynchronous READY
setup time
1)
t
58
SR
15
–
15
–
ns
Asynchronous READY
hold time 1)
t
59
SR
0
–
0
–
ns
Async. READY hold time
after RD, WR high (Demul-
tiplexed Bus)
2)
t
60
SR
0
0 +
t
c
+2
t
A + tF
2)
0
TCL - 25
+
t
c +2tA + tF
2)
ns



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