ST10F167 datasheet(45/69 Pages) STMICROELECTRONICS

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ST10F167

20.4 A/D Converter Characteristics

DD =5 V ± 5%, VSS =0 V, TA = -40 to +85 °C

4.0 V

≤ V

AREF ≤ VDD+0.1 V, VSS-0.1 V ≤ VAGND ≤ VSS+0.2 V

Sample

time

and

conversion

time

the

ST10F167’s ADC are programmable. Table 20.3

shows the timing calculations.

Notes 1:VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conver-

sion result in these cases will be X000H or X3FFH, respectively.

2:During the sample time the input capacitance CI can be charged/discharged by the external

source. The internal resistance of the analog source must allow the capacitance to reach its final

voltage level within tS. After the end of the sample time tS, changes of the analog input voltage

have no effect on the conversion result.

Values for the sample clock tSC depend on programming and can be taken from the table above.

3:This parameter includes the sample time tS, the time for determining the digital result and the

time to load the result register with the conversion result.

Values for the conversion clock tCC depend on programming and can be taken from the table

above.

4:This parameter depends on the ADC control logic. It is not a real maximum value, but rather a

Table 20.2

A/D Converter Characteristics

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

max.

Analog input voltage range

AIN

AGND

AREF

V1)

Sample time

–

2) 4)

Conversion time

–

CC + tS

+ 4TCL

3) 4)

Total unadjusted error

TUE

–

+ 3

LSB

Internal resistance of reference

voltage source

AREF

–

CC /165

-0.25

Ω

tCC in [ns] 6) 7)

Internal resistance of analog

source

ASRC

–

S / 330

-0.25

Ω

tS in [ns] 2) 7)

ADC input capacitance

AIN

–

Table 20.3

Sample and Conversion Time Calculations

ADCON.15|14

(ADCTC)

Conversion clock

ADCON.13|12

(ADSTC)

Sample clock t

TCL * 24

Reserved, do not use

CC *2

TCL * 96

CC *4

TCL * 48

CC *8

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