ST10F167 datasheet(49/69 Pages) STMICROELECTRONICS

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ST10F167

20.5.4 Phase Locked Loop

When pin P0.15 (P0H.7) is high (‘1’) during reset

the on-chip phase locked loop is enabled and pro-

vides the CPU clock. The PLL multiplies the input

frequency by 4 (i.e. fCPU =fXTAL * 4). With every

fourth transition of fXTAL the PLL circuit synchro-

nizes the CPU clock to the input clock. This syn-

chronization is done smoothly, i.e. the CPU clock

frequency does not change abruptly.

Due to this adaptation to the input clock the fre-

quency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter

of fCPU which also effects the duration of individual

TCLs.

The timings listed in the AC Characteristics that re-

fer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective

circumstances.

The actual minimum value for TCL depends on the

jitter of the PLL. As the PLL is constantly adjusting

its output frequency so that it remains locked to the

applied input frequency (crystal or oscillator) the

relative deviation for periods of more than one TCL

is lower than for one single TCL (see formula and

figure below).

For a period of

N * TCL the minimum value is com-

puted using the corresponding deviation DN:

where

N = number of consecutive TCLs and

≤ N ≤ 40.

So for a period of 3 TCLs (i.e.

N = 3):

This is especially important for bus cycles using

waitstates and e.g. for the operation of timers, se-

rial interfaces, etc. For all slower operations and

longer periods (e.g. pulse train generation or

measurement, lower baudrates, etc.) the deviation

caused by the PLL jitter is negligible.

Figure 20.5

Approximated Maximum PLL Jitter

TCL

mi n

TCL

NO M * 1lD N l )

100

–

(

N15

) %

[]

⁄

–

(

43 15

⁄

–

3.8%

TCL

min

TCL

NO M

3.8 100

⁄

–

()

TCL

NO M

0.962

24.1nsec@f

CP U

20MHz

()

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

≤ N ≤ 40 and 10MHz ≤ f

CPU ≤ 20MHz.

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