ST10 datasheet(16/65 Pages) STMICROELECTRONICS

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ST10C167

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Hardware traps are exceptions or error conditions

that arise during run-time. They cause immediate

non-maskable system reaction similar to a stan-

dard interrupt service (branching to a dedicated

vector table location).

The occurrence of a hardware trap is additionally

signified by an individual bit in the trap flag regis-

ter (TFR). Except when another higher prioritized

trap service is in progress, a hardware trap will

interrupt any actual program execution. In turn,

hardware trap services can normally not be inter-

rupted by standard or PEC interrupts.

Table 3 shows all of the possible exceptions or

error conditions that can arise during run-time:

Table 3 : Exceptions or error conditions that can arise during run time

Exception Condit ion

Trap

Flag

Trap

Vector

Location

Trap

Number

Trap

Priority

Reset Functions:

Hardware Reset

Software Reset

Watchdog Timer Overflow

RESET

00’0000h

00h

III

Class A Hardware Traps:

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008h

00’0010h

00’0018h

02h

04h

06h

Class B Hardware Traps:

Undefined Opcode

Protected Instruction Fault

Illegal Word Operand

Access

Illegal Instruction Access

Illegal External Bus

Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028h

0Ah

Reserved

[2Ch –3Ch]

[0Bh – 0Fh]

Software Traps

TRAP Instruction

Any [00’0000h– 00’01FCh]

in steps of 4h

Any

[00h – 7Fh]

Current CPU

Priority

VII - INTERRUPT SYSTEM (continued)

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