ST10 datasheet(41/65 Pages) STMICROELECTRONICS

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ST10C167

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Notes 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be

X000H or X3FFH, respectively.

During the sample time the input capacitance CI can be charged/dischargedby the external source. The internal resistance of the

analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the

analog input voltage have no effect on the conversionresult. Values for the sample clock tSC depend on programming and can be taken

from the table above.

3. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with

the conversion result. Values for the conversion clock tCC depend on programming and can be taken from the table above.

4. This parameter is fixed by ADC control logic.

5. TUE is tested at VAREF = 5.0V, VAGND = 0V, VCC = 4.9V. It is guaranteed by design characterization for all other voltages within the

defined voltage range. The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum of

2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.

During the reset calibration sequence the maximum TUE may be

±4 LSB.

6. During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference

voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results

from the programmed conversion timing.

7. Partially tested, guaranteed by design characterization.

Sample time and conversion time of the ST10C167’s ADC are programmable. The table below should be

used to calculate the above timings.

XX.4 - AC characteristics

Test waveforms

ADCON.15|14 (ADCTC)

Conversion clock tCC

ADCON.13|12 (ADSTC)

Sample clock tSC

TCL * 24

tCC

Reserved, do not use

tCC *2

TCL * 96

tCC *4

TCL * 48

tCC *8

Figure 9 : Input output waveforms

Figure 10 : Float waveforms

2.4V

0.45V

Test Points

0.2VDD+0.9

0.2VDD-0.1

AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.

Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

Timing

Reference

Points

VLoad +0.1V

VLoad -0.1V

VOH -0.1V

VOL +0.1V

VLoad

VOL

VOH

For timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.

It begins to float when a 100mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20mA).

XX - ELECTRICAL CHARACTERISTICS (continued)

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