ST52F510 datasheet(96/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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15 SERIAL PERIPHERAL INTERFACE (SPI)

15.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master, one or more slaves, or a system, in which

devices may be either masters or slaves.

SPI is normally used for communication between

the ICU and external peripherals or another ICU.

Refer to the Pin Description section in this

datasheet for the device-specific pin-out.

15.2 Main Features

Full duplex, three-wire synchronous transfers

Master or slave operation

Four master mode frequencies

Maximum slave mode frequency = CKM/4.

Four programmable master bit rates

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision flag protection

Master mode fault protection capability.

15.3 General description

SPI is connected to external devices through 4

alternate pins:

– MISO: Master In / Slave Out pin

– MOSI: Master Out / Slave In pin

– SCK: Serial Clock pin

–SS: Slave select pin (if not done through soft-

ware)

Figure 15.1 SPI Master Slave

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 15.1

The MOSI pins are connected together as the

MISO pins. In this manner, data is transferred

serially between master and slave (most significant

bit first).

When the master device transmits data to a slave

device via the MOSI pin, the slave device responds

by sending data to the master device via the MISO

pin. This implies full duplex transmission with both

data out and data in synchronized with the same

clock signal (which is provided by the master

device via the SCK pin).

The transmitted byte is replaced by the byte

received and eliminates the need for separate

transmit-empty and receiver-full bits. A status flag

is used to indicate that the I/O operation is

complete.

Four possible data/clock timing relationships may

be chosen (see Figure 15.4), but master and slave

must be programmed with the same timing mode.

15.4 Functional Description

Figure 15.2 shows the serial peripheral interface

(SPI) block diagram.

This interface contains 3 dedicated registers:

– A Control Register (SPI_CR)

– A Status Register (SPI_STATUS_CR)

– A Data Register for transmission (SPI_OUT)

– A Data Register for reception (SPI_IN)

15.4.1 Master Configuration.

In a master configuration, the serial clock is

generated on the SCK pin.

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

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