ST52F510 datasheet(19/106 Pages) STMICROELECTRONICS

19 / 106 page

ST52F510/F513/F514

19/106

Each interrupt level has its own set of flags, which

is saved in the Flag Stack during interrupt

servicing. These flags are restored from the Flag

Stack automatically when a RETI instruction is

executed.

If the ICU was in normal mode before an interrupt,

after the RETI instruction is executed, the normal

flags are restored.

Note: A subroutine CALL is a normal mode

execution. For this reason a RET instruction,

consequent to a CALL instruction, doesn’t affect

the normal mode set of flags.

Flags are not cleared during context switching and

remain in the state they were in at the exit of the

last interrupt routine switching.

The Carry flag is set when an overflow occurs

during arithmetic operations, otherwise it

cleared. The Sign flag is set when an underflow

occurs during arithmetic operations, otherwise it is

cleared.

The flags, related to the current context, can be

checked by reading the FLAGS Input Register 38

(026h).

Figure 2.3 Multiplication

2.2 Arithmetic Logic Unit

The 8-bit Arithmetic Logic Unit (ALU) performs

arithmetic calculations and logic instructions such

as: sum, subtraction, bitwise AND, OR, XOR, bit

set and reset, bit test and branch, right/left shift and

rotate (see the Chapter 9 Instruction Set for further

details).

In addition, the ALU of ST52F510/F513/F514 can

perform multiplication (MULT) and division (DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values); the

division instruction addresses the MSB of the

dividend (the LSB is stored in the next address):

the result and remainder are stored in these source

addresses (see Figure 2.3 and Figure 2.4).

In order to manage signed type values, the ALU

also performs addition and subtraction with offset

(ADDO

and

SUBO).

These

instructions

respectively subtract and add 128 to the overall

result, in order to manage values logically in the

range between -128,127.

Figure 2.4 Division

RAM

000h

001h

002h

j+1

j-1

0FFh

0FDh

0FEh

REG. j

REG. i

LSB

MSB

16 Bit

RAM

j+1

j-1

REG. j

REG. j+1

REMAINDER

QUOTIENT

REG. i

i-1

i+1

000h

001h

002h

0FFh

0FDh

0FEh

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