ST52F510 datasheet(25/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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3.7 Configuration Registers & Option Bytes

The

ST52F510/F513/F514

Configuration

Registers bench consists of a file of 8-bit registers

that allows the configuration of all the ICU blocks.

The registers are located inside the block they

configure in order to obtain greater flexibility and

modularity in the design of new family devices. In

the Configuration Registers, each bit has a

peculiar use, so the logic level of each of them

must be considered.

Some special configuration data, that needs to be

load at the start-up and not further changed, are

stored in Option Bytes. These are loaded only

during the device programming phase. See Table

3.3 and Section 4 for a detailed description of the

Option Bytes.

The Configuration Registers are readable and

writable; the addresses refer to the same register

both in read and in write. In order to access the

Configuration Register the user can work in

several

modes

utilizing

the

following

instructions:

LDCI:

loads

the

immediate

value

the

Configuration Register specified and is the most

commonly used to write configuration data.

LDCR:

loads

the

Configuration

specified with the contents of the specified

configuration.

LDCE:

loads

the

Configuration

specified with the contents of the specified

Program/Data Memory location, allowing the

configuration data to be taken from a table.

LDCNF: loads the

specified with the contents of the Configuration

the configuration of the device (permitting safe

run-time modifications).

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Configuration Registers is shown in Table 3.4.

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