ST72260G datasheet(93/171 Pages) STMICROELECTRONICS

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ST72260G, ST72262G, ST72264G

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

11.5.7 Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a write to the SCIDR register).

0: Data is not transferred to the shift register

1: Data is transferred to the shift register

Note: Data will not be transferred to the shift reg-

ister unless the TDRE bit is cleared.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a

frame containing Data, a Preamble or a Break is

complete. An interrupt is generated if TCIE=1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a write to the SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Pre-

amble or a Break.

Bit 5 = RDRF

Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR

SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a Idle Line is de-

tected. An interrupt is generated if the ILIE=1 in

the SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs).

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the SCICR2

access to the SCISR register followed by a read to

the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will

not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected

on a received frame. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error is detected

1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

Bit 0 = PE

Parity error.

This bit is set by hardware when a parity error oc-

curs in receiver mode. It is cleared by a software

sequence (a read to the status register followed by

an access to the SCIDR data register). An inter-

rupt is generated if PIE=1 in the SCICR1 register.

0: No parity error

1: Parity error

TDRE

RDRF

IDLE

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