ST72260G datasheet(28/171 Pages) STMICROELECTRONICS

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ST72260G, ST72262G, ST72264G

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7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro-

vides the following features:

Hardware interrupts

Software interrupt (TRAP)

Nested or concurrent interrupt management

with

flexible

interrupt

priority

and

level

management:

– Up to 4 software programmable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non-maskable events: RESET and TRAP

This interrupt management is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

each interrupt vector (see Table 4). The process-

ing flow is shown in Figure 17

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers

of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Table 4. Interrupt Software Priority Levels

Figure 17. Interrupt Processing Flowchart

Interrupt software priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= interrupt disable)

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

EXECUTE

INSTRUCTION

INTERRUPT

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