STLC1502 datasheet(20/81 Pages) STMICROELECTRONICS

20 / 81 page

STLC1502

20/81

MIAB: Memory Interface Address Bus

MIWE: Memory Interface Write Enable

MIAA: Memory Interface Access Active (nCAS)

MISA: Memory Interface Setup Active (nRAS)

After the power-up the CPU must configure each SDRAM device, i.e. perform precharge-refresh-mode register

set procedure.

6.3.1.3 Memory Configuration register

Memory configuration registers are used to setup parameters that are same for all banks:

PWS: Power save mode

•

If PWS bit is set to’1’, the next refresh cycle will set the memory devices in the self-refresh mode.

•

The memories will exit the self-refresh mode, when the PWS mode is set to’0’.

TYPE: Memory type:

•

The TYPE bit is used to select a type of the external memory.

•1 - SDRAM

•0 - EDO

B3EN: Bank 3 enable

B2EN: Bank 2 enable

B1EN: Bank 1 enable

B0EN: Bank 0 enable

•

The bank enable bits are used to enable each bank separately.

•

If an AHB transfer is accessing a disabled bank, the DRAM Controller will return the error response

to the AHB master.

REFR: Refresh period

•

The REFR value is used to determine the refresh period. The period can be set in the 1 us steps.

•

REFR Refresh Period

•

00000000 Refresh is disabled

•

00000001 Refresh period is 1us

•

00000010 Refresh period is 2us

•.

•

11111111 Refresh period is 255us

6.4 DMA Controller

•

The DMA controller is intended to be used with the Ethernet switch block to transfer Ethernet frames

between the Ethernet switch buffers and memory.

•

The DMAC needs initialization before starting operation. During operation it does not need interven-

1 0

Reserved

PWS

TYPE

B3EN

B2EN

B1EN

B0EN

REFR

STLC1502 데이터시트(PDF) 20 Page - STMicroelectronics

STLC1502 데이터시트(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

데이터시트 다운로드

링크 URL