STLC1502 datasheet(35/81 Pages) STMICROELECTRONICS

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STLC1502

7.2 Watchdog Timer

STLC1502 contains a Watchdog timer. This timer is used to reset the ARM7 in case of a software deadlock.

The watchdog timer generates a hot reset when it overflows which will restart the ARM, but the code will

not be downloaded again. The timer should be cleared by the software before it overflows.

It is based on a 8 bit counter which is clocked by a slow signal coming from a 17 bit prescaler clocked by

the system clock.

So the elapsing time of the watchdog timer depend on the system clock:

SYS_CLK:

13MHz => 2.58 seconds

26MHz => 1.29 seconds

39MHz => 0.86 seconds

52MHz => 0.64 seconds

This peripheral consists of a timer that continue to run and to reset the core if the software doesn’ t clear

it before it elapses. The software can clear or disable the timer by writing the WDOG_CONTROL register

7.2.1 Watch Dog Register Map [0x0C500000]

TimerBase + 0x28

Timer3Control

R/W

Timer3Control. The Control regis-

ter provides enable/disable, mode

and prescale configurations for the

timer (see Figure 10).

TimerBase + 0x0C

Timer3Clear

Timer3Clear. Writing to the Clear

location clears an interrupt gener-

ated by the counter timer.

TimerBase + 0x30

Timer4Load

R/W

Timer4Load. The Load register

contains the initial value of the timer

and is also used as the reload

value in periodic timer mode.

TimerBase + 0x34

Timer4Value

Timer4Value. The Value location

gives the current value of the timer.

TimerBase + 0x38

Timer4Control

R/W

Timer4Control. The Control regis-

ter provides enable/disable, mode

and prescale configurations for the

timer (see Figure 10).

TimerBase + 0x3C

Timer4Clear

Timer4Clear. Writing to the Clear

location clears an interrupt gener-

ated by the counter timer.

Address

R/W

Notes

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