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6.7 TIC-Test Interface Controller

The Test Interface Controller (TIC) is a state machine that provides an AMBA AHB bus master for system test.

It reads test write and address data from the external data bus TESTBUS (XD), and uses the External Bus In-

terface (part of the DRAM Controller) to drive the external bus with test read data, allowing the use of only one

set of output tristate buffers onto TESTBUS.

The TIC is used to convert externally applied test vectors into internal transfers on the AHB bus. A three-wire

external handshake protocol is used, with two inputs controlling the type of vector that is applied and a single

output that indicates when the next vector can be applied. Typically the TIC is the highest priority AMBA bus

master, which ensures test access under all conditions. The TIC model supports address incrementing and con-

trol vectors. This means that the address for burst transfers can automatically be generated by the TIC.

6.8 AHB-ASB bridge

The APB bridge is the only bus master on the Advanced Peripheral Bus. In fact, the APB bridge is also a slave

on the AHB. The bridge unit converts ASB transfers into APB transfers. On the APB bus only 16 bits wide data

accesses are permitted. 32 bit wide and 8 bit wide transfers are not supported. All the APB peripherals decodes

all the 16 bits of the PA bus.

APB decoding scheme

Every area is 128k x 16 bits but the area actually available is 32k x 16 due to the fact that the address lines on

the APB bus are 16 (PA(15:0)). That means that in every area dedicated to the several block on the APB bus

only the first FFFF is usable.

7.0 APB bus

The APB bus is a 16 bits data and 16 bits address bus. The blocks attached on this bus are described in the

following sections while the memory area is reported in the following figure.

All the addresses in the APB space are word aligned (addresses are multiples of four)

APB decoder space

PA(15:0)

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