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STLC5466 데이터시트(PDF) 104 Page - STMicroelectronics |
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STLC5466 데이터시트(HTML) 104 Page - STMicroelectronics |
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104 / 130 page ![]() STLC5466 104/130 Figure 1-27: MHDLC clock generation FRAME A CLOCK A FRAME B CLOCK B Select A or B INT1 RESET Supervision Deactivation FSCGCI FSCV* SYN1 SYN0 Frame Clock HCL CLOCK SELECTION CLOCK ADAPTATION Ref. Clock To the internal A or B Selected DCLK (SELB) (BSEL) MHDLC (CSD) Clock General Configuration Register (GCR) Clock Lack Detection from 250m s At RESET FRAME A and CLOCK A are selected |
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