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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STLC5466 데이터시트(PDF) 108 Page - STMicroelectronics |
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STLC5466 데이터시트(HTML) 108 Page - STMicroelectronics |
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108 / 130 page  STLC5466 108/130 2.3 GCI interface Figure 2-3: Sychronization signals delivered by the Multi-HDLC Parameter T min T typical T max t1 DCLK Clock Period if 4096 kHz (3072) DCLK Clock Period if 2048 kHz (1536) Id CLOCKA or B (T min) 244 (325) 488 (651) Id CLOCKA or B (T max) t3 DCLK to FSCG 20 t5 Duration FS 244 125000-244 t6 DCLK to data 50 pF DCLK to data 100 pF 50 100 t7 Set up time data/DCLK 20 t7 Hold time data/DCLK 20 The four Multiplex Configuration Registers are at zero (no delay between FS and Multiplexes). DCLK delivered DIN 0/8 FSCG delivered DOUT 0/7, CB Bit0, Time Slot 0 by the Multi-HDLC by the Multi-HDLC CH 0 CH 1 CH7 DIN4/5 125ms MON D C/I AE B1 B2 DOUT4/5 FS received by the Multi-HDLC t3 t3 t6 t7 t7 t1 If FSCG connected to FS |
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