Electrical Characteristics

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

25

2.5.5.2

CLKIN to CLKOUT Skew

2.5.5.3

DMA Data Transfers

Table 17 describes the DMA signal timing.

The DREQ

according to the timings in Table 17. Figure 12 shows synchronous peripheral interaction.

Table 16. CLKOUT Skew

No.

Characteristic

Units

20

Rise-to-rise skew

0.0

0.95

ns

21

Fall-to-fall skew

–1.5

1.0

ns

23

CLKOUT phase (1.1 V, 133 MHz)

•

Phase high

•

Phase low

2.2

2.2

—

—

ns

ns

24

CLKOUT phase (1.1 V, 100 MHz)

•

Phase high

•

Phase low

3.3

3.3

—

—

ns

ns

Notes:

1.

A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.

2.

Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.

3.

CLKOUT skews are measured using a load of 10 pF.

4.

CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.

Figure 11. CLKOUT and CLKIN Signals.

Table 17. DMA Signals

No.

Characteristic

Ref = CLKIN

Units

Min

Max

37

DREQ set-up time before the 50% level of the falling edge of REFCLK

5.0

—

ns

38

DREQ hold time after the 50% level of the falling edge of REFCLK

0.5

—

ns

39

DONE set-up time before the 50% level of the rising edge of REFCLK

5.0

—

ns

40

DONE hold time after the 50% level of the rising edge of REFCLK

0.5

—

ns

41

DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

0.5

7.5

ns

CLKIN

CLKOUT

20

21