MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freescale Semiconductor

30

2.5.7

TDM Timing

Figure 16. DSI Synchronous Mode Signals Timing Diagram

Table 21. TDM Timing

No.

Characteristic

Expression

1.1 V Core

Units

Min

Max

300

TDMxRCLK/TDMxTCLK

16

—

ns

301

TDMxRCLK/TDMxTCLK high pulse width

(0.5

± 0.1) × TC

7

—

ns

302

TDMxRCLK/TDMxTCLK low pulse width

(0.5

± 0.1) × TC

7

—

ns

303

TDM receive all input set-up time

1.3

—

ns

304

TDM receive all input hold time

1.0

—

ns

305

2.8

—

ns

306

TDMxTCLK high to TDMxTDAT/TDMxRCLK output

—

10.0

ns

307

2.5

—

ns

308

TDMxTCLK high to TDmXTDAT/TDMxRCLK output high

—

10.7

ns

309

—9.7

ns

310

2.5

—

ns

Notes:

1.

Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

Devices operating at 300 MHz are limited to a maximum TDMxRCLK/TDMxTCLK frequency of 50 MHz.

2.

Values are based on 20 pF capacitive load.

3.

When configured as an output, TDMxRCLK acts as a second data link. See the MSC8113 Reference Manual for details.

4.

Values are based on 10 pF capacitive load.

HCLKIN

HA[11–29] input signals

All other input signals

HD[0–63] output signals

HTA output signal

HD[0–63] input signals

120

127

123

126

127

122

121

131

130

129

128

133

135

134

132

HCID[0–4] input signals

125

127

127

124