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MSC8113 데이터시트(PDF) 34 Page - Freescale Semiconductor, Inc |
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MSC8113 데이터시트(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 44 page ![]() MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Freescale Semiconductor 34 2.5.10.2 MII Mode Timing 2.5.10.3 RMII Mode Table 25. MII Mode Signal Timing No. Characteristics Min Max Unit 803 ETHRX_DV, ETHRXD[0–3], ETHRX_ER to ETHRX_CLK rising edge set-up time 3.5 — ns 804 ETHRX_CLK rising edge to ETHRX_DV, ETHRXD[0–3], ETHRX_ER hold time 3.5 — ns 805 ETHTX_CLK to ETHTX_EN, ETHTXD[0–3], ETHTX_ER output delay 1 14.6 ns Figure 23. MII Mode Signal Timing Table 26. RMII Mode Signal Timing No. Characteristics 1.1 V Core Unit Min Max 806 ETHTX_EN,ETHRXD[0–1], ETHCRS_DV, ETHRX_ER to ETHREF_CLK rising edge set-up time 1.6 — ns 807 ETHREF_CLK rising edge to ETHRXD[0–1], ETHCRS_DV, ETHRX_ER hold time 1.6 — ns 811 ETHREF_CLK rising edge to ETHTXD[0–1], ETHTX_EN output delay. 3 12.5 ns Figure 24. RMII Mode Signal Timing Valid ETHRX_CLK ETHRX_DV ETHRXD[0–3] ETHTX_CLK ETHRX_ER ETHTX_EN ETHTXD[0–3] Valid Valid ETHTX_ER 803 804 805 Valid ETHREF_CLK ETHCRS_DV ETHRXD[0–1] ETHRX_ER 807 806 ETHTX_EN ETHTXD[0–1] Valid Valid 811 |
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