Electrical Characteristics

MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

19

2.5.4.1

Power-On Reset (PORESET) Pin

2.5.4.2

Reset Configuration

The MSC8113 has two mechanisms for writing the reset configuration:

•

Through the direct slave interface (DSI)

•

Through the system bus. When the reset configuration is written through the system bus, the MSC8113 acts as a

configuration master or a configuration slave. If configuration slave is selected, but no special configuration word is

written, a default configuration word is applied.

Configuration Mode and boot and operating conditions:

•

RSTCONF

•

CNFGS

•

DSISYNC

•

DSI64

•

CHIP_ID[0–3]

•

BM[0–2]

•

SWTE

•

MODCK[1–2]

Table 11. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On

Reset

(PORESET)

Hard Reset (HRESET)

Soft Reset (SRESET)

External only

External or Internal

(Software Watchdog or

Bus Monitor)

External

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Section 2.5.4.1 for details).

Yes

NoNoNo

SPLL state reset

Yes

No

No

No

System reset configuration write through

the DSI

Yes

NoNoNo

System reset configuration write though

the system bus

Yes

Yes

No

No

HRESET driven

Yes

Yes

No

No

SIU registers reset

Yes

Yes

No

No

IPBus modules reset (TDM, UART,

Timers, DSI, IPBus master, GIC, HS, and

GPIO)

Yes

Yes

Yes

Yes

SRESET driven

Yes

Yes

Yes

Depends on command

SC140 extended cores reset

Yes

Yes

Yes

Yes

MQBS reset

Yes

Yes

Yes

Yes