M306V2EEFS datasheet(143/271 Pages) RENESAS

143 / 271 page

Rev.1.40

Oct 06, 2004 page 143 of 269

M306V2ME-XXXFP, M306V2EEFP

Item

Standard Clock Mode

High-speed Clock Mode

Setup time

5.35

µs (53.5 cycles)

1.85

µs (18.5 cycles)

Hold time

4.9

µs (49 cycles)

2.4

µs (24 cycles)

Set/reset time for BB flag

3.75

µs (37.5 cycles)

0.85

µs (8.5 cycles)

(7) START condition generation method

When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register

to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit

counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and

BB bit set timing are different in the standard clock mode and the high-speed clock mode. Refer to

Figure 2.11.42 for the START condition generation timing diagram, and Table 2.11.13 for the START

condition/STOP condition generation timing table.

(8) STOP condition generation method

When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register

for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be

generated. The STOP condition generation timing and the BB flag reset timing are different in the

standard clock mode and the high-speed clock mode. Refer to Figure 2.11.43 for the STOP condition

generation timing diagram, and Table 2.11.13 for the START condition/STOP condition generation

timing table.

Fig. 2.11.42 START condition generation timing diagram

Fig. 2.11.43 STOP condition generation timing diagram

Table 2.11.13 START condition/STOP condition generation timing table

Note: Absolute time at BCLK = 10 MHz. The value in parentheses denotes the number of BCLK cycles.

I2Ci status register write signal

Set time for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

I2Ci status register write signal

Reset time

for

BB flag

Hold time

Setup

time

SCL

SDA

BB flag

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