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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M306V2EEFS 데이터시트(PDF) 145 Page - Renesas Technology Corp |
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M306V2EEFS 데이터시트(HTML) 145 Page - Renesas Technology Corp |
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145 / 271 page  Rev.1.40 Oct 06, 2004 page 145 of 269 M306V2ME-XXXFP, M306V2EEFP (10) Address data communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit ad- dressing format. The respective address communication formats is described below. s 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2Ci address register. At the time of this comparison, address comparison of the RBW bit of the I2Ci address register is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 2.11.45, (1) and (2). s 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2Ci address register. At the time of this comparison, an address ___ comparison between the RBW bit of the I2Ci address register and the R/W bit which is the last bit of ___ the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2Ci status register is set to “1.” After the second-byte address data is stored into the I2Ci data shift register, make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2Ci address register ___ to “1” by software. This processing can match the 7-bit slave address and R/W data, which are re- ceived after a RESTART condition is detected, with the value of the I2Ci address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure 2.11.45, (3) and (4). |
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