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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M306V2EEFS 데이터시트(PDF) 146 Page - Renesas Technology Corp |
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M306V2EEFS 데이터시트(HTML) 146 Page - Renesas Technology Corp |
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146 / 271 page  Rev.1.40 Oct 06, 2004 page 146 of 269 M306V2ME-XXXFP, M306V2EEFP (11) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2Ci clock control register. ➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “0816” in the I2Ci control register. ➄ Set the address data of the destination of transmission in the high-order 7 bits of the I2Ci data shift register and set “0” in the least significant bit. ➅ Set “F016” in the I2Ci status register to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ➆ Set transmit data in the I2Ci data shift register. At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆. ➈ Set “D016” in the I2Ci status register. After this, if ACK is not returned or transmission ends, a STOP condition will be generated. (12) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2Ci clock control register. ➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “0816” in the I2Ci control register. ➄ When a START condition is received, an address comparison is made. ➅ •When all transmitted address are“0” (general call): AD0 of the I2Ci status register is set to “1”and an interrupt request signal occurs. •When the transmitted addresses match the address set in ➀: ASS of the I2Ci status register is set to “1” and an interrupt request signal occurs. •In the cases other than the above: AD0 and AAS of the I2Ci status register are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2Ci data shift register. ➇ When receiving control data of more than 1 byte, repeat step ➆. ➈ When a STOP condition is detected, the communication ends. |
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