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HD404849FS 데이터시트(PDF) 25 Page - Renesas Technology Corp |
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HD404849FS 데이터시트(HTML) 25 Page - Renesas Technology Corp |
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25 / 127 page ![]() HD404849 Series 23 Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts ( INT 0, INT1, INT2, INT3): There are four external interrupt signals. External Interrupt Request Flags (IF0–IF3: $000, $001, $022): IF0 and IF1 are set when the signals input to INT 0 and INT1 are falling, and IF2 and IF3 are set when the signals input to INT2 and INT3 are rising or falling, as listed in table 5. The INT 2 and INT3 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0–IF3: $000, $001, $022) IF0–IF3 Interrupt Request 0No 1 Yes Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 0 0 W ESR10 1 0 W ESR11 Detection edge selection register 1 (ESR1: $026) ESR11 0 1 ESR10 0 1 0 1 INT2 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection ESR13 0 1 ESR12 0 1 0 1 INT3 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection Note: Both falling and rising edges are detected. ** * Figure 12 Detection Edge Selection Register 1 (ESR1) |
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