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HD404849FS 데이터시트(PDF) 28 Page - Renesas Technology Corp |
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HD404849FS 데이터시트(HTML) 28 Page - Renesas Technology Corp |
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28 / 127 page ![]() HD404849 Series 26 Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 13. Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0No 1 Yes Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 2) IFS Interrupt Request 0No 1 Yes Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS: $023, Bit 3) IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in table 17. |
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