7516 datasheet(39/90 Pages) RENESAS

39 / 90 page

Rev.1.01

Jul 01, 2003

page 39 of 89

7516 Group

sPrecautions when using multi-master I2C-

BUS interface

(1) Read-modify-write instruction

The precautions when the read-modify-write instruction such as

SEB, CLB etc. is executed for each register of the multi-master

I2C-BUS interface are described below.

• I2C data shift register (S0: address 002B16)

When executing the read-modify-write instruction for this regis-

ter during transfer, data may become a value not intended.

• I2C address register (S0D: address 002C16)

When the read-modify-write instruction is executed for this regis-

ter at detecting the STOP condition, data may become a value

not intended. It is because H/W changes the read/write bit

(RWB) at the above timing.

• I2C status register (S1: address 002D16)

Do not execute the read-modify-write instruction for this register

because all bits of this register are changed by H/W.

• I2C control register (S1D: address 002E16)

When the read-modify-write instruction is executed for this regis-

ter at detecting the START condition or at completing the byte

transfer, data may become a value not intended. Because H/W

changes the bit counter (BC0-BC2) at the above timing.

• I2C clock control register (S2: address 002F16)

The read-modify-write instruction can be executed for this regis-

ter.

• I2C START/STOP condition control register (S2D: address

003016)

The read-modify-write instruction can be executed for this regis-

ter.

(2) START condition generating procedure using multi-master

1. Procedure example (The necessary conditions of the generat-

ing procedure are described in Items 2 to 5 below.

LDA —

(Taking out of slave address value)

SEI

(Interrupt disabled)

BBS 5, S1, BUSBUSY (BB flag confirming and branch process)

BUSFREE:

STA S0

(Writing of slave address value)

LDM #$F0, S1

(Trigger of START condition generating)

CLI

(Interrupt enabled)

BUSBUSY:

CLI

(Interrupt enabled)

2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag

confirming and branch process.

3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page ad-

dressing instruction for writing the slave address value to the

I2C data shift register.

4. Execute the branch instruction of Item 2 and the store instruc-

tion of Item 3 continuously, as shown in the procedure example

above.

5. Disable interrupts during the following three process steps:

• BB flag confirming

• Writing of slave address value

• Trigger of START condition generating

When the condition of the BB flag is bus busy, enable interrupts

immediately.

(3) RESTART condition generating procedure

1. Procedure example (The necessary conditions for the proce-

dure are described in items 2 to 4 below.)

Execute the following procedure when the PIN bit is “0.”

LDM #$00, S1

(Select slave receive mode)

LDA —

(Take out of slave address value)

SEI

(Disable interrupt)

STA S0

(Write slave address value)

LDM #$F0, S1

(Trigger RESTART condition generation)

CLI

(Enable interrupt)

2. Select the slave receive mode when the PIN bit is “0.” Do not

write “1” to the PIN bit. Neither “0” nor “1” is specified as input to

the BB bit.

The TRX bit becomes “0” and the SDA pin is released.

3. The SCL pin is released by writing the slave address value to

the I2C data shift register.

4. Disable interrupts during the following two process steps:

• Write slave address value

• Trigger RESTART condition generation

(4) Writing to I2C status register

Do not execute an instruction to set the PIN bit to “1” from “0” and

an instruction to set the MST and TRX bits to “0” from “1” simulta-

neously. Because it may enter the state that the SCL pin is

released and the SDA pin is released after about one machine

cycle. Do not execute an instruction to set the MST and TRX bits

to “0” from “1” simultaneously when the PIN bit is “1.” Because it

may become the same as above.

(5) Process of after STOP condition generating

Do not write data in the I2C data shift register S0 and the I2C sta-

tus register S1 until the bus busy flag BB becomes “0” after

generating the STOP condition in the master mode. Because the

STOP condition waveform might not be normally generated.

Reading to the above registers do not have the problem.

•

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