7516 datasheet(29/90 Pages) RENESAS

29 / 90 page

Rev.1.01

Jul 01, 2003

page 29 of 89

7516 Group

Function

In conformity with Philips I2C-BUS

standard:

10-bit addressing format

7-bit addressing format

High-speed clock mode

Standard clock mode

In conformity with Philips I2C-BUS

standard:

Master transmission

Master reception

Slave transmission

Slave reception

16.1 kHz to 400 kHz (at

φ = 4 MHz)

Table 7 Multi-master I2C-BUS interface functions

Item

Format

Communication mode

System clock

φ = f(XIN)/2 (high-speed mode)

φ = f(XIN)/8 (middle-speed mode)

MULTI-MASTER I2C-BUS INTERFACE

The multi-master I2C-BUS interface is a serial communications cir-

cuit, conforming to the Philips I2C-BUS data transfer format. This

interface, offering both arbitration lost detection and a synchro-

nous functions, is useful for the multi-master serial

communications.

Figure 27 shows a block diagram of the multi-master I2C-BUS in-

terface and Table 7 lists the multi-master I2C-BUS interface

functions.

This multi-master I2C-BUS interface consists of the I2C address

the I2C control register, the I2C status register, the I2C start/stop

condition control register and other control circuits.

When using the multi-master I2C-BUS interface, set 1 MHz or

more to

φ.

Note: Mitsubishi Electric Corporation assumes no responsibility for in-

fringement of any third-party’s rights or originating in the use of the

connection control function between the I2C-BUS interface and the

ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control regis-

ter (002E16).

Fig. 27 Block diagram of multi-master I2C-BUS interface

✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components

an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

SCL clock frequency

I2C address register

b7b0

SAD6SAD5SAD4 SAD3 SAD2 SAD1 SAD0RWB

Noise

elimination

circuit

Address comparator

I2C data shift register

Data

control

circuit

System clock (

φ)

Interrupt

generating

circuit

Interrupt request signal

(IICIRQ)

MST TRX BB PIN

AL AAS AD0 LRB

b7b0

TISS

10BIT

SAD

ALS

BC2BC1BC0

S1D

Bit counter

circuit

Clock

control

circuit

Noise

elimination

circuit

b7b0

ACK

BIT

FAST

MODE

CCR4CCR3 CCR2 CCR1 CCR0

Internal data bus

Clock division

S0D

circuit

ES0

SIS

I2C start/stop condition

control register

SIP SSC4 SSC3 SSC2 SSC1 SSC0

I2C clock control register

I2C status register

S2D

TSEL

I2C clock control register

S1D I C control register

Serial data

(SDA)

Serial

clock

(SCL)

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