M66596FP datasheet(43/131 Pages) RENESAS

43 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 43 of 127

DCP control register [DCPCTR]

<Address: 60H>

BSTS SUREQ

SQCLR SQSET SQMON

CCPL

PID

Bit

Name

Function

S/W

H/W

Note

BSTS

Buffer Status

0: Buffer access is disabled.

1: Buffer access is enabled.

3.4.1.1

*5)

SUREQ

Request to transmit SETUP packet

A SETUP packet is transmitted by setting this

bit to 1.

0: Invalid

1: transmit SETUP packet

R/W(1) R/W(0) 3.6.1

*11)

14-9 Nothing is placed here. These should be fixed at “0”.

SQCLR

Toggle Bit Clear

0: Invalid

1: Specifies DATA0

R(0)/

W(1)

3.3

*7),*8)

SQSET

Toggle Bit Set

0: Invalid

1: Specifies DATA1

R(0)/

W(1)

3.3

*7),*8)

SQMON

Toggle Bit Confirm

0: DATA0

1: DATA1

3.3

*9)

5-3 Nothing is placed here. These should be fixed at “0”.

CCPL

Control Transfer End enabled

0: Invalid

1: The control transfer is ended.

R(0)/

W(1)

R/W(0) 3.6.2

*6)

1-0 PID

Response PID

00: NAK response

01: BUF response (in keeping with the buffer

state)

10: STALL response

11: STALL response

R/W

3.6

*10)

<<Notes>>

*5) The direction of buffer access, writing or reading, is depend on setting of ISEL bit.

*6) In the peripheral mode the CCPL bit is cleared to “0” right after the SETUP token has been received.

In the host mode this bit should be set “CCPL=0”(not use).

*7) If the SQSET bits and the SQCLR bits of the DCPCTR register and the PIPExCTR registers are being changed

in succession (the PID sequence toggle bits of multiple pipes are being changed in succession), an access cycle of

at least 200 ns is required.

*8) The SQCLR bit and SQSET bit should not both be set to “1” at the same time. Before operating either bit,

“PID=NAK” should be set.

*9) In the Peripheral mode the SQMON bit is initialized to “1” by the controller right after the SETUP token of the

control transfer has been received.

*10) In the peripheral mode the PID bit is cleared to “00” right after the SETUP token has been received. And at the

time of occurring of a transmission error etc., PID bits are set up by the controller and transmission is ended.

*11) When SUREQ bit is set to 1, it is set to 0 by H/W after SETUP transaction sending out.

While the SUREQ bit is 1, do not write in USBREQ, USBVAL, USBINDX, and a USBLENG register.

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